The Lowest On-Resistance and Robust 130nm BCDMOS Technology implementation utilizing HFP and DPN for mobile PMIC applications

BCD technology has been the workhorse of several critical products in the mobile market. Aggressive design rule and architectural modifications are being exploited to achieve significant improvements in the high voltage device performance such as low Ron.sp and high BVDSS which are crucial for improved switching efficiency and product robustness. In order to meet the requirements, we applied High temperature oxide field plate (HFP) structure with heavily doped poly and Double RESURF with P-Burid Layer (PBL) for the performance. And we used the self-aligned P-Body process and the decoupled plasma nitridation (DPN) gate oxide process for the robust reliability. From these evaluations, for the critical 12V N-LDMOS device, we have been able to achieve an ON-resistance of $3.0\ \mathbf{m}\mathbf{\Omega}-\mathbf{mm}2$ with BVDSS of 21.5V which is considered world-class. The new features make our 130nm BCD technology a powerful platform for future mobile PMIC.