An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.