NOR flash memory device having multi-level memory cell, and bit value detection method

NOR flash memory device with - a memory cell (1a, 1b), which is designed to store two or more bits of data (MSB_D, LSB_D) - a reference voltage generator (40a, 40b), which is designed to generate a plurality of different reference voltages (DG_H, DG_M, DG_L) and to provide parallel, - a sense amplifier (10a, 10b), which is designed to detect the values ​​of the two or more data bits stored sequentially on the basis of a reference current, the height of which is determined by the different reference voltages (DG_H, DG_M, DG_L) and sequentially (in a sense node SA0) to make, - a selection circuit (30a, 30b), which is designed to select which determines the various reference voltages, the height of the reference current, and to receive the detected value of a first (MSB_D) the stored bits of data, and depending on a selection signal (LSB_L, LSB_H) for provide sampling of the value of a second (LSB_D) of the stored data bits, - a reference current-supplying circuit (14a, 15a; 14b, 35b) to provide the corresponding to the selected reference voltage reference current, the plurality of different reference voltages are supplied in parallel and is supplied to the selection signal of the selection circuit and to the sense node (SA0) is coupled, and - a Abtastknotenvorladeschaltung (13a), which is designed to charge the sensing node (SA0) to a predetermined voltage level after the sense amplifier (10a) has detected the value of the first bit (MSB) of the two or more bits of data and before the value of the second bits detected.