Early Evaluation of ESD Robustness of RF ICs on System-Level

We demonstrate a design methodology that combines on-wafer Transmission Line Pulse testing and a simulation setup with a behavioral model for the radio frequency integrated circuit (RF IC). Our methodology enables the early assessment of system-level ESD robustness during the design of the RF IC. The residual stress of an RF port is evaluated using different parallel inductors, which act as a protection element. We show that a TLP pulse width of 10 ns is sufficient to estimate the system-level robustness.