A 6.4G LLR/s 8×8 64-QAM soft-output MIMO detector with lattice reduction preprocessing

Multiple-input multiple-output (MIMO) communication is an important technique to increase the transmission capacity, but the increased antenna number does not necessarily increase the throughput because of more antenna interference and decoding complexity. An iterative detector-and-decoder (IDD) can effectively improve transmission performance by exchanging reliability information such as log likelihood ratio between a MIMO detector and a error-correction-code decoder, but the IDD reduces the throughput because of the iteration loop. Therefore, this paper proposes a lattice-reduction-aided (LRA) soft-output K-best detector to eliminate the iteration loop and devises an effective method to calculate the reliable information. The proposed 8 × 8 LRA soft-output K-best detector achieves a better performance than the 8 × 8 MIMO detectors in the literature. The proposed detector was designed and implemented using TSMC 90nm 1P9M CMOS process. The post-layout results show that the detector chip achieves a throughput of 6.4G LLRs/sec at its maximum frequency of 133.3 MHz with 64-QAM modulation.