KM3NeT Front-end electronics upgrade: CLBv3 and PBv3

High efficiency, high reliability and low power consumption are the main challenges for the design of the front-end electronics of the KM3NeT neutrino telescope. The so-called Phase II of the KM3NeT project, to be started after the completion of the ongoing Phase I, is currently under design. It presents an opportunity to enhance the performance of the front-end electronics. The present article describes the main modifications under study for the KM3Net Phase II frontend electronics boards, the Central Logic Board and the Power Board. These modifications aim for a higher efficiency and reliability, and a lower power consumption and price.