Materials challenges for III-V/Si co-integrated CMOS

This review focuses on material challenges associated with III-V co-integration with Si for future CMOS. There is a huge volume of literature on this topic as implementation of III-V monolithic integration with Si has been the holy grail for last four decades; targeting a wide range of applications including RF devices, LEDs, lasers, photo-detectors and the like. The key drivers have been the cost reduction, scalability with Si wafer diameter, and accessibility to highly scaled integrated circuits next to III-V devices. With the current focus on CMOS the pace of progress on monolithic integration has accelerated by leaps and bounds partly because of its vast impact on CMOS scaling, and partly due to the aggressive CMOS roadmap requirements. The discussion below concentrates on In 0.53 Ga 0.47 As channel which is the dominant III-V material being pursued for future technology. Despite the narrow focus, fundamental and engineering challenges posed by this material encompass a broad range of material topics including epitaxial growth, crystallographic defects and their dynamics during growth and subsequent processing, clever device architecture to alleviate adverse impact of defects on device leakage, and innovative engineering for material improvement.