A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS

Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220 mW for 58.6-pJ energy consumption per sample.