A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBTs, MESFETs, and Si BJTs. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2 Gb/s 1:8 demultiplexer are described. These multigigabit LSIs have been achieved mainly by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (f/sub max/), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSIs are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding. >