Machine-learning assisted fast critical area analysis

Critical Area Analysis (CAA) is an established DFM tool to assess the defect limited yield of a semiconductor design. However, several factors limit the usefulness of this tool for advanced technology nodes at 28nm and below. Specifically for metal design layers, retargeting has been a successful measure to improve defect limited yield. Retargeting will opportunistically widen lines and space them further apart where possible. Since retargeting happens during the tapeout phase it is not visible to the designer. A critical area analysis solely based on design shapes therefore underestimates defect limited yield by a substantial amount. Furthermore, CAA computation time for large designs has grown exponentially as the grid size of designs has been shrunk with each technology node. For a large design, CAA computation can take weeks and consume large computational resources. We have come up with a new and fast methodology to compute CAA that takes retargeting into account and thus gives far more realistic estimates of defect limited yield. Our method takes advantage of the fact that even large designs usually consist of millions of repetitions of similar design blocks that will report very similar CAA metrics. By training a machine learning model on representative design snippets one can come up with a flow that estimates the CAA of the full chip and runs very fast.