A process for producing a well structure for high-K-stacked capacitors in DRAMs and FRAMs

A method for manufacturing a high-K-stacked capacitor in a semiconductor memory device comprising the steps of: - forming a contact hole (106) in a one transistor overlying SiO - filling the contact hole (106) with polysilicon (107) to form a Polyplugs (108) in the contact opening; - etching a recess (109) in the exposed surface of the Polyplugs (108); - producing a planarized surface using the chemical-mechanical polishing, wherein a barrier layer (110) and a first metal layer (111) to fill the recess; - applying a second metal or metal oxide layer (112) and structuring the second metal layer to form the lower part of an electrode (113), which is in contact with the recess located in the metal; and - depositing a high-K dielectric (214) and a third metal or metal oxide layer (215) for forming an upper portion of the stacked capacitor electrode, characterized, in that the barrier layer (110) and the first metal layer (111) are applied in-situ.