Delay Calculator and Timing Analysis

When introducing a new technology, the transient behaviour of the circuits available in the circuit library have to be established early in the design cycle. The logic designer needs to know the performance of the critical path (the longest path in the machine, and therefore the path that determines the machine cycle). For this calculations the delay of all the circuits offered in the circuit library have to be known as early as possible in the design cycle (see “3.5 Timing Analysis and Verification” on page 177). Figure 193 shows a 2-way AND INVERT (2WAI) circuit in CMOS technology. The input A1 of the circuit is assumed to be in the “high” state. The other input is used as the switching input by applying the input voltage as shown in Figure 194. The corresponding output voltage of the circuit is Vout. C is a lumped capacity representing the output load i.e. wiring and fan-in capacitance of the following circuit(s). Figure 194 shows the transient behaviour of the input and output voltage of the 2WAI circuit. It also shows the four delay times which are to be calculated.