Inductance Modeling of Interconnections in 3-D Stacked-Chip Packaging

This letter explores the inductance of interconnections including through-silicon vias (TSVs) and redistribution layers (RDLs) in 3-D stacked-chip packaging. It is described that the common summing method of partial inductances will result in some deviations from the full inductance. Then, the inductances of TSVs and RDLs are, respectively, calculated and are verified by a commercial electromagnetic simulator. The modified formulas are proposed for the more accurate full inductance model, which is derived from different design physical parameters of the interconnections. The side effect of a general summing method can be reduced a lot by our proposed analytical model.