Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping

Abstract Hardware monitoring information can be used during system runtime to increase system lifetime and reliability. Examples of such monitoring information are power, temperature, and the aging status of processors. They provide the system with relevant information about the current hardware health. Such information is especially crucial in resource-aware computing concepts that introduce self-organizing behavior to deal with large MPSoCs (Multi-Processor Systems-on-Chip): For resource-aware computing, resources are allocated according to the current requirements. To find suitable resource-application pairs and achieve system targets like optimizing the utilization, current hardware status must be considered during resource allocation. To evaluate and optimize resource allocation strategies during the design phase, FPGA prototyping is often required before its implementation in ASIC. The evolution of power, temperature and aging differ between ASIC implementation and FPGA prototype. The FPGA prototype should react on sensor data characterized from the target ASIC design instead of FPGA’s hardware status. This paper describes the design of an emulated ASIC Temperature and Power Monitoring system (eTPMon) for FPGA-based prototyping. The emulation approach for power monitors is based on an instruction-level energy model. For emulating temperature monitors, a thermal RC model is used. eTPMon can supply MPSoC prototypes with the hardware status information (power and temperature of the cores) needed for efficient load distribution, achieving resource-aware computing targets. Based on the eTPMon data, different operating strategies and control targets were evaluated for a 2-tile resource-aware MPSoC system. Values provided by eTPMon are usable for extracting information about the aging of processors, which can be used for increasing the system lifetime.