A semiconductor device comprising metallization stack with a very small ε (ULK) reduced interaction between chip and package

A semiconductor device comprising: a metallization (260) with a metal wiring layer (220, 230) over a substrate (201) is formed, the metal wiring layer (230) comprises a metal line (235) laterally in a porous dielectric material (231) is embedded, wherein the metallization (260) further includes a via layer (240) containing a via (245) in communication with the metal conduit (235) in connection, and the laterally into a non-porous dielectric material (241) along the height of the via (245) is embedded and the non-porous dielectric material (241) an etch stop layer (242) and at least one further material that is formed at least locally at the via (245), said at least one further material material regions (241A, 241B) forms, each of which is laterally embedded in a further porous dielectric material; anda bump structure (210) which is adapted to be connected to a complementary contact of a package substrate structure using a lead-free solder material.