FPM 15.2: A Voltage Reduction Technique for Digital Systems

ncircuit adjusts the internal supply voltage to the lowest value compalible with chip speed requirements, taking temperature and technology parameters into account. Beside enhancing reliability, this ncw technique also allows power savings, important for battery-operated systems such as lap-top computers and portable instrumentation or radio­ communication systems. A digital chip is characterized by a critical path. Reducing the supply voltage will caUse this path to slow until it CaUses mal­ function. The general voltage-reductio n technique presented in Figure 1 is based on regulation of the supply voltage of an ""l uiva ­ lent critical path', a small circuit with delay-Vdd properties pro­ portional to those of the actual critical path. The output of this equivalent critical path is compared to the output of a second identical equivalent critical path which is connected to the full supply voltage, and serves as a reference. 1n a first order approxi­ mation, the ratio of the delay of a critical path to the period of a ring oscillator is a constant that depends only on the number of gates, the dimensions of the transistors and the load capacitances. This means that a ring oscillator can be used as an equivalent critical path for all digital cirCUits. Moreover, by changing the sup­ ply voltage of a ring oscillator (VeO), the frequency chan!,;c,. The v