A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed

Advancing to 45 nm 1 Gb NOR flash requires new process and design techniques. The process developments of SACS, tungsten source rail, and better pump capacitors increase cell size and reduce overall die size. The design techniques of two-transistor row decoders, a new sensing architecture, more effective charge pumps and program performance improvements enable multilevel flash cells to meet a die size of 30 mm 2 and 5 MB/s program speed in 45 nm technology.