Determination of the effect of processing steps on the CMOS compatibility of a surface micromachined pressure sensor

A surface micromachining process for the fabrication of a pressure sensitive field effect transistor (FET), compatible with complementary metal oxide semiconductor (CMOS) processing, has been established in which residual membrane stress can be tuned without changing the underlying CMOS operation. The residual membrane stress must be controlled at a low tensile value for optimum operation of the pressure FET. Controlling this residual stress involves the development of suitable processing conditions, and the effect of alteration from standard CMOS processing on the underlying circuitry must be evaluated. The effects of different processing conditions for a surface micromachined polysilicon pressure sensing membrane on the CMOS characteristics are presented. Variations in the polysilicon sensor layer deposition and implant conditions in the surface micromachining process and back-end CMOS interlayer dielectric reflow were examined as these strongly influence the residual stress in the membrane. The electrical characteristics for devices that had only CMOS processing did not vary significantly from the electrical characteristics of devices that had the pressure sensor surface micromachining layer processing.