Geometry scaling issues originated by extrinsic stress in SiGe HBTs

The influence of stress induced by shallow trench isolation (STI) on the geometry scaling of DC parameters in SiGe HBTs is studied. It is shown that smaller devices experience higher stress effect due to the STI than larger devices. In the presence of stress, the scaling of transfer current with geometry can not be fully accounted by separating it into area and perimeter components. STI stress effect is studied here, by varying emitter-STI spacing and emitter geometry parameters. Stress is shown to affect current gain and BVCEO as well. Based on the Vbe shift for smaller geometries, stress seen by the device is estimated.