Improving microcontroller (MCU) immunity performance to system-level ESD/EFT testing through PCB system co-design methodology

In this paper we described a PCB system co-design modeling methodology that can be implemented, early in the system design phase, to improve system-level immunity performance in the presence of IEC electromagnetic transient disturbances. The methodology is validated through correlation to laboratory measurements on a TI MSP430™ microcontroller PCB system.