LOW POWER CMOS BINARY COUNTER USING CONVENTIONAL FLIP - FLOPS

The performance of the proposed technique with the conventional clock gated and conventional non clock gated FFs were designed in 0.18-µm CMOS technology. The comparison and selection was based on the operation principle and the structure, since each type of FFs takes on a different behaviour in terms of redundant transitions depending on the factors. For the conventional counters, the amount of power consumed in FFs and logic gates used for evaluating the next counter values for implementing the clock gating are measured, including the power consumption and the clock inputs of the FFs and the logic gates. For the proposed counters, the amount of power consumed in FFs and LCGs are measured. The experimental result indicates that the proposed synchronous counter achieves a power saving and device count reduction.