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Optimization of CMOS power-cell layout for improving junction breakdown
Optimization of CMOS power-cell layout for improving junction breakdown
2014
Ockgoo Lee
Jeonghu Han
Kyu Hwan An
Hyoungsoo Kim
Joonhui Hur
Kiseok Yang
Kyutae Lim
Chang-Ho Lee
Joy Laskar
Keywords:
Electronic engineering
Time-dependent gate oxide breakdown
CMOS
Computer science
Electrical engineering
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