Old Web
English
Sign In
Acemap
>
Paper
>
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
2021
Mangal Deep Gupta
Rajeev K Chauhan
Keywords:
Field-programmable gate array
Frequency divider
Arithmetic
pseudo random bit generator
Computer science
Period (gene)
Variable (computer science)
Correction
Source
Cite
Save
Machine Reading By IdeaReader
25
References
1
Citations
NaN
KQI
[]