Study and improvement of anomalous interface states of metal‐oxide‐semiconductor structures induced by rapid thermal post‐oxide annealing

Anomalous interface states were caused by post‐oxide rapid thermal annealing in an n+ polycrystalline silicon metal‐oxide‐semiconductor capacitor. These anomalous interface states have been investigated using high/low frequency capacitance/gate voltage (C/V) measurements. An additional annealing process (450 °C, 30 min in 90% N2/10% H2 mixed gas) was found to improve the anomalous interface states. The improved results were identified using a constant current injection stress test.