Challenging the paradigm of monitor reduction to achieve lower product costs

Increasing competition within the semiconductor industry is forcing many manufacturers to consider and implement aggressive cost reduction measures across many operations. In addition, defect inspection steps are often perceived as being "non-value add" metrology operations, and are frequently the primary focus for further monitor reduction and/or elimination to reduce operational costs. In this paper, the highlights of a joint research project between Intel Corporation and KLA-Tencor Corporation are discussed, with the primary focus on the use of advanced statistical and stochastic models that utilize defect, yield, and financial inputs to hilly characterize the overall costs associated with the monitoring and control of random defect excursions in an advanced semiconductor manufacturing process. The use of the KLA-Tencor Sample Planner/sup TM/ program provides a sophisticated methodology to evaluate the overall cost impacts associated with proposed monitor reduction and monitor elimination activities. The analysis illustrated the importance of assessing the yield impact due to defect excursions when pursuing further monitor reduction and/or elimination. In addition, the project results confirmed that the current inspection sampling plan that was being utilized by Intel (with minor modifications), provided a cost-effective allocation of the existing defect inspection capacity. Consequently, the Sample Planner program proved to be an effective tool in challenging the paradigm of monitor reduction to achieve lower product costs in an advanced semiconductor manufacturing line.