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LSSD at speed scan test and Source synchronous DDR interface test by 1149 using on chip PLL
LSSD at speed scan test and Source synchronous DDR interface test by 1149 using on chip PLL
2006
Toshihiko Yokota
Keywords:
Source-synchronous
Double data rate
Chip
Electronic engineering
Phase-locked loop
Computer science
Computer hardware
Correction
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