High Resolution Time-to-Digital Converter Design with Anti-PVT-Variation Mechanism

This paper presents a 5.4-ps resolution with anti-PVT-variation Time-to-Digit Converter (TDC) using 90-nm CMOS technology. This proposed TDC uses the two-step architecture in which the first stage is Buffer Delay line to get a wide dynamic range and then the delayed start and stop signals are given to the second stage (Vernier Delay line) by an edge detector for higher resolution. This whole two-step architecture is monitored by a PVT Detector to resist Process, Voltage, Temperature (PVT) variation. The proposed TDC archives 5.4 ps resolution with 2 ps delay variation and 890 ps of dynamic range. INL and DNL are simulated to be 1 LSB and 0.8 LSB, respectively.