Simulation and Reliability Study of Cu/Low‐k Devices in Flip‐chip Packages

The package impact to the mechanical integrity of the low dielectric constant (low‐k) dielectrics back end of the line (BEOL) structure has been proven to be significant in recent publications. This work reports a simulation study of the package‐induced delamination in low‐k structures by interfacial fracture mechanics combined with multi‐scale finite element method. The numerical simulation is validated by reliability test results of low‐k devices in different flip‐chip package configurations. The modeling result is compared to reliability test data of low‐k devices in organic, ceramic flip‐chip packages, and good correlation is found. Feasibility of flip‐chip packaging for low‐k devices is demonstrated. The risk of low‐k delamination on different package configurations is rated based on both reliability data and numerical simulations.