SWIFT® Semiconductor Packaging Technology

The continued scaling of transistor geometries for semiconductor devices has been placing an increased demand on the next‐level interconnect technologies. A new, innovative chip‐last high density fan‐out (HD‐FO) structure called Silicon Wafer Integrated Fan‐out Technology (SWIFT) packaging incorporates conventional fan‐out waferlevel packaging (FO‐WLP) processes with leading‐edge, thin film patterning techniques to bridge the gap between through‐silicon via technology and traditional FO‐WLP packages. For smartphones and wearable devices, 3D package‐on‐package (PoP) structures have become the standard for application processor (AP) and DRAM integration. SWIFT packaging is also capable of conformal shielding, which is increasingly requested for laminate‐based system in package (SiP) modules. In addition to the AP and SiP markets, SWIFT packaging has applications in the networking and high performance graphics segments. This chapter focuses on the comparison of the chip‐last HD‐FO technology process with both exposed‐die PoP and fan‐in PoP for signal integrity, power integrity, and impedance matching.