Follower voltage flipped with FGMOS transistors for low-voltage and low-power applications

In this paper a new follower voltage flipped (FVF), with floating gate CMOS transistors (FGMOS) is proposed. To demonstrate that the proposed structure with FGMOS transistors is a very suitable structure to solve problems for analog cells design with low voltage and low power, theoretical steps design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The design consists of three FGMOS transistors and one current mirror. Simulated results are compared with those obtained by theoretical analysis. The results show that the proposed FVF in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 81μW, a THD of 3% with a 0.5V p-p 1GHz sinewave input and a 30KHz load resistance.