Electromigration Failure Time Model of General Circuit-Like Interconnects

The majority of interconnects in an integrated circuit is composed of via-terminated segments that are connected to atomic sinks or reservoirs. In this paper, we investigate electromigration failure of Cu/low-k conductors with active (current carrying) sinks and reservoirs, as well as configurations where currents flow into or out of a common via. We show that when steady-state stress profiles are combined with current densities, an accurate picture of electromigration failure for circuit-like interconnects emerges. Voiding locations are in general dependent on length and current ratios between active and sink/reservoir segments, leading to a rich variety of voiding behavior. A modeling methodology is developed to predict both voiding locations and failure time distributions in the presence of arbitrary configurations of active sinks, reservoirs, and common vias.