Characteristics of 0.25 µm Ferroelectric Nonvolatile Memory with a Pb(Zr, Ti)O3 Capacitor on a Metal/Via-Stacked Plug

A 0.25-µm ferroelectric memory with 16 kbit-cell array was fabricated. A Pb(Zr, Ti)O3 (PZT) capacitor was formed on a metal(Al)/via(W)-stacked plug using low temperature metal organic chemical vapor deposition (MO-CVD). The backend process had no effect on the PZT capacitor properties. The 1×1 µm2 capacitor shows good fatigue and imprint endurance. Signal voltage on the bit-line in the cell array is 1.06 V for switching and 0.58 V for unswitching. These results agree well with the pulse-response measurement of the parallel capacitor. However, the signal voltage deviation becomes larger with the capacitor size reduction. The 16 kbit-cell array shows the column access time of 50 ns and the minimum operation voltage of 1.6 V.