Speed Enhancement in the Performance of Two Phase Clocked Adiabatic Static CMOS Logic Circuits

In this paper, we have addressed one very important issue of the unconventional adiabatic logic circuits. As compared to the bulk CMOs, the former has more delay which affects the performance. it has been aimed to reduce the delay of Two Phase Clocked Adiabatic Static CMOS Logic (2PASCL). So, we are proposing a circuit in which we would compromise some amount of the power with that of a delay in the circuit. The aim is to improve the delay which is general problem with all adiabatic logic families. The proposed circuit has been implemented with NAND and NOT gate and have been simulated in CADENCE gpdk180 CMOS process. The analysis has been done in terms of delay parameters and power consumption. The results show substantial improvement in the delay at the cost of power savings.