A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability

A power-efficient single node upset hardened latch design with in-situ error detection capability, EDSL, is proposed in this paper for reliability improvement against soft errors. Our simulation results show that the proposed EDSL design can not only recover from any incurred single node upset, but also provide in-situ error detection capability when the latch output is upset. When compared with state-of-the-art error-detection-based and SNU resilient designs, the proposed EDSL latch can achieve up to 72.25% and 79.74% reduction of power-delay-product respectively, which clearly shows the effectiveness of the proposed method.