Stress Analysis on Ultra Thin Ground Wafers

Grinding wafers is a well established process for thinning wafers down to 100 µm for use in smart cards and stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in Si wafers thinned down to ~20∝m by means of an IR time-of-flight like technique. Such aggressive thinning is a requirement for high density vias interconnect, stacked die packaging and flexible electronics. We found that the thinning process used did not add significant stress value on the thinned wafer.