Utilizing parallelism of TMR to enhance power efficiency of reliable ASIC designs

Due to aggressive scaling, reliability issues influence the design process of integrated circuits more and more. A well known technique to tackle these issues represents Triple Modular Redundancy (TMR). It strongly improves reliability of a design at the expense of at least tripled area and power consumption. In this contribution, we propose an enhanced TMR approach that significantly decreases the power overhead of conventional TMR designs. Therefore, the control logic was modified so as to switch between a TMR mode and a parallel mode. This parallel mode allows the circuit to operate with decreased frequency without losing performance by taking advantage of the parallelism offered by the tripled design. Achieved results of investigations on the ISCAS benchmark circuits show power savings of up to 50 % with a small reliability penalty compared to a conventional TMR approach for permanent failures. We also propose strategies how to utilize both operating modes in order to balance the design concerning reliability and power consumption requirements at runtime.