Dual-mask model-based proximity correction for high-performance 0.10-μm CMOS process

Selective strong phase shift mask techniques, whereby a phase-shift mask exposure is followed by a binary mask exposure to define a single pattern, present unique capabilities and problems. First, there is the proper exposure balance and alignment of the two masks. Second, there is the challenge of performing optical proximity correction that will account for two overlaying exposure models and masks. This is further complicated by the need to perform multiple biasing and adjustments that are often required for development processes. In this paper, we present results for applying a new OPC correction technique to a dual exposure binary and phase-shift mask that have been used for development of 100 nm CMOS processes. The correction recipe encompasses two models that were anchored to optimized processes (exposure, NA, and ?). The correction to the masks also utilized boolean techniques to perform selective biasing without destroying the original hierarchical structure. CMOS technology utilizes isolation with pitches of active device regions below 0.4 ?m. The effective gate length on silicon is in the range of 0.08 to 0.18 ?m. Patterning of trench openings and gate regions are accomplished using deep-UV lithography.