Design of RISC-V processor based on Chisel

2021 
In recently years, RISC-V′s popularity in the field of processors is not only due to its open-source and extensible instruction set architecture attributes, but also thanks to Chisel, an agile design language tailored by UC Berkeley, greatly reducing the threshold of processor design.A multi-core RISC-V chip with extended instruction coprocessor based on Chiselis designed and implemented in this paper. Compared with the traditional hardware design language, the design and integration time of hardware IP is compressed by more than 50%. At the same time, relying on rich template resources, it can quickly complete the global optimization design that affects the overall performance of the processor, such as topology interconnection, timing segmentation, and cross-clock domain conversion, reducing the iteration time of chip verification and implementation by more than 30%. The open-source processor agile development has explored effective technical means.
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