A parallel logic simulation framework: study, implementation, and performance

We present a parallel logic simulation framework aiming at more then one simulation language, not only some special. After investigating a number of research issues in parallel logic simulation, we study these key techniques including general parallelization method, code portioning, and practical synchronization algorithm. Based on ArchSim (a system-level parallel simulation platform), the framework can run on heterogeneous computing environments. By using the framework, we parallelize two logic simulation languages: SystemC and Verilog. Then, we design a pipelined multi-stage benchmark to evaluate the framework. Encouraging test results indicate that speedup gradually approaches to the linear growth with the computation complexity or the number of stages increasing. Another SoC application shows that speedup of the parallel logic simulation framework is almost the same with the shared-memory scheme. To sum up, by using our framework, a logic simulation language is easily parallelized to gain an excellent speedup.