Progression of Logic Device and DTCO to enable advance scaling (Conference Presentation)

CMOS technology scaling is enabled by multiple logic transistor architecture change from Planner to FinFET to Nanosheet and most recently Forksheet and CFET. Every architecture change has significant impact on the power-performance-area (PPA) scaling of any system on chip (SOC). A comprehensive Design-Technology-optimization (DTCO) methodology is needed to analyze this impact. In this paper technology scaling impact of this architecture change along with lithographic scaling will be analyzed from standard Cell to Block Level Place-Route to realize realistic PPA estimate.