Combined effects of BTI, HCI and OFF-State MOSFETs Aging on the CMOS Inverter Performance

In this work, the degradation of the transistors in a CMOS inverter under the various biasing configurations in a complete operation cycle and their impact on the circuit performance are experimentally studied. The relationships between transistors parameters (threshold voltage and mobility) and circuit specifications shifts (peak current and inversion voltage) are explained in terms of the different device aging mechanisms that are active depending on the voltages at the circuit terminals. Moreover, the combined effects of the different aging mechanisms sequentially activated (such as BTI, HCI and OFF-state), at device and circuit levels, emphasizing the role of the OFF-state degradation, are also discussed.