A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications

This paper presents an hardware/software communication mechanism, well suited for telecommunication oriented multi-processors system-on-chip (MP-SoC). It allows the system designer to map a parallel, multi-threaded software application, onto a generic multi-processors architecture. This hardware architecture can contain a variable number of programmable processors, and a variable number of dedicated hardware co-processors, sharing the same address space. The software application is written in C, in the form of a set of parallel and communicating tasks. The software tasks use a specific communication library, containing two communication primitives, to access one or several shared memory communication buffers implementing software FIFOs. For a given MWMR FIFO, any producer or consumer can be implemented in hardware or software. Validation and performance evaluation are done by ”cycle accurate, bit accurate” SystemC simulation, using the SoCLib [5] library of simulation models. The generic MWMR communication channel supporting both hardware or software producer or consumer, makes possible to decide quite late whether a task should be implemented in software or hardware.