Twin-register architecture for an AI processor

Abstract We have developed a twin-register architecture to improve the backtracking speed of Prolog programs. The twin-register architecture is designed to realize a virtual infinite register set. The features of the architecture are: (1) only a small amount of hardware is needed including a pair of register-files; and, (2) data transfer between the register and the memory is automatically executed. A register saving/restoring operation and the Prolog instruction are executed in parallel in order to reduce the overhead of memory accesses. We have implemented the twin-register architecture into our AI processor IP704 to show its effectiveness. Experimental results have shown that the execution time of 8-Queen program is reduced by 15% in the case of the twin-register architecture, as compared with that in the case of the ordinary architecture in which saving/restoring are done by software. Also, we have found the architecture is useful for register saving/restoring of the procedure CALL/RETURN in general procedural programs.