A configurable CMOS multiplier/divider for analog VLSI

The design of a simple CMOS operational-amplifier-based multiplier/divider is presented. The 2 operational amplifier and 6 MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuit in analog signal processing are discussed. The multiplier/divider circuit is insensitive to MOS intrinsic parasitic capacitances. It is sensitive to operational amplifier finite unity-gain bandwidth. This sensitivity may be mitigated using the configurability property of the circuit. Experimental results are provided to support some of the theoretical claims. >