Performance of front-end readout system for PHENIX RICH

A front-end electronics system have been developed for the ring imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-plane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 /spl mu/s per event. The design specifications and test results of the system are presented in this paper.