A NOVEL DESIGNFOR COMPUTATION OFALL TRANSFORMS INH.264/AVC DECODERS

Inthispaper, we design a novelarchitecture for computing alltransforms required inH.264/AVChigh profile decoder. Thisflexible architecture design can computealltransforms including 8 and4-point integer transforms aswellas4and2-point Hardamard transforms suchthatwe canreduce theimplementation chiparea dramatically. With8pixels/cycle throughput, this proposed design cancomplete thecomputation in95clock cycles with8X8inverse transform involved or54clock cycles without 8x8 inverse transform foronemacroblock. Simulation results showthat theimplemented areais18.5k gatecounts, andthemaximumclock frequency is125MHz. Forthereal-time requirement, thearchitecture candeal with allexisted frame sizes in4:2:0 format. Forexample, ifthis architecture isoperated at 106 MHz, itachieves 4096x2304(a30 frames/sec.