Design of a digital IP for 3D-IC die-to-die clock synchronization
2017
In this paper the design of a novel IP for 3D IC die-to-die clock synchronization is presented. The proposed design offers notable benefits over the conventional dual DLL based architectures for 3D IC clock synchronization. Simulation results of the IP are presented with GLOBALFOUNDRIES 14nm finFET library, and Through-Silicon Via (TSV) technology.
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