Cell array structure test in EEPROM reliability assessment at an early process development stage

Abstract We present a simple structure and a simple test to obtain important information on EEPROM cells’ reliability, such as the threshold voltage distribution of the cell array and its evolution during a bake retention experiment. Both intrinsic and extrinsic characteristics can be determined, thanks to the clamping effect of the select transistor in series to each memory transistor. The method is useful not only during the early process development stage, but also as a process monitor.