Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes

We have fabricated FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved with a guiding layer. The self-assembly process is integrated with an existing CMOS process flow using conventional tools on a full wafer level. This is the first demonstration of functional circuits fabricated using self-assembly at the (n+1) th patterning level where n ≥ 1.