Embedded charge investigation: industry concerns and metrology solutions

As described by the ITRS roadmap [1], introduction of next generation processes in semiconductor fabrication continually requires tighter control in order to insure optimal device characteristics. Recent process development has shown an increased amount of charged layers, which in turn affects the inline critical dimension scanning electron microscope's (CD-SEM) ability to generate quality measurements thereby impacting process control. This paper reports on the investigation of techniques to measure and compensate for this charge dynamically to yield quality measurements. New capabilities of the CD-SEM were evaluated and tested at various process steps including processing steps not measured by the CD SEM. This capability not only means the CD-SEMs are essentially immune to charged layer affects but the capability can also be used to feedback to other tool-sets suspected of causing the charge build-up. These charge measurements help provide an understanding on how the device performance might be impacted. In order to establish charged wafer monitoring in the future along with feedback loops, studies of the reproducibility and the persistency of the charge across sequential processes in the back-end layers have been made. Studies were also conducted to determine the origin of the charge by observing the distribution before and after known problematic process steps.